A concurrent testing technique for digital circuits
نویسندگان
چکیده
منابع مشابه
Testing Technique for Digital Circuits
In this paper, we present a method of testing digital circuits during normal operation. The resources used to perform on-line testing are those which are inserted to alleviate the off-line testing problem. The off-line testing resources are modified such that during system operation they can also observe the normal inputs and outputs of a combinational circuit under test. The normal inputs to t...
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ACKNOWLEDGMENTS First and foremost, I would like to express my gratefulness to God for all his blessings. I am indebted to my advisor, Dr. Bharat L. Bhuva who has always been there to support, advice and direct me in my work. I can count the number of days that I have not been in his office without a question to ask. He has been very patient with me and has always given me ideas when results we...
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In this paper we present a few fundamental results related to the problems of characterization and detection of intermittent faults in digital circuits, which, up to now, have been almost totally ignored. This problem is important since in many technologies intermittency is a predominant mode of failure. We first discuss various new classes of fault modes. We then introduce a Markov model for a...
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* This work was done at Stanford-CRC and was supported by King Fahd University of Petroleum and Minerals. It was also supported by DARPA under contract No. DABT63-97-C-0024 (ROAR project). The authors would like to thank Chien-Mo Li and Chao-Wen Tseng for their help. Abstract Many digital circuits have constraints on the logic values a set of signal lines can have. In this paper, we present two...
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ژورنال
عنوان ژورنال: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
سال: 1988
ISSN: 0278-0070,1937-4151
DOI: 10.1109/43.16803